1. Field of the Invention
The invention relates in general to a semiconductor integrated circuit (IC) structure, and more particularly to a buried wiring line structure.
2. Description of the Related Art
Polysilicon is usually used as a conductive material for fabricating structures in semiconductor devices such as gate electrodes and bit lines. When the size of the semiconductor device arrives at the deep submicron level, the requirement for a high operating rate creates some device stability problems.
A conventional method for forming a polysilicon wiring line is to deposit a polysilicon layer on a provided substrate by low pressure chemical vapor deposition (LPCVD). A part of the polysilicon layer is etched until the substrate is exposed. The remaining polysilicon layer is thus used as a gate electrode or a bit line. However, the step of etching the polysilicon layer has some disadvantages; for example, the etching process is complicated and the polysilicon layer formed on the substrate occupies layout space. Furthermore, polysilicon grain size, which is affected by thermal processes, affects the resistance of the polysilicon layer. If the resistance of the polysilicon line cannot be controlled accurately, the quality of semiconductor devices thus fluctuates.
Moreover, an etching process is performed to remove a part of the polysilicon layer while forming the polysilicon line. If the polysilicon layer is not removed completely, polysilicon remaining on the substrate may cause unintended connections. If the polysilicon layer is over-etched, the substrate may be damaged, which can cause defects.
A conventional buried bit line is developed to resolve the problems described above. The method of forming the buried bit line comprises the step of implanting a dopant into a substrate. However, the dopant in the substrate easily diffuses due to thermal processes after forming the buried bit line so that the distribution of the dopant cannot be controlled. Resistance of the buried bit line is thus unstable.